The present invention relates to a semiconductor memory device with an improved load circuit.
FIG. 1 shows a modified and simplified circuit of a floating gate memory device shown in FIG. 1 of U.S. Pat. No. 4,223,394. In this circuit, a detector 15 detects storage data in a floating gate memory 3 (n floating gate memories 3-1 to 3-n) selected by a decoder 1 and produces a detection signal corresponding to the detected storage data. A sensing amplifier 7 compares a reference voltage from a reference voltage generator 11 with the detection signal, and produces a binary signal corresponding to the storage data of the floating gate memory 3 selected by the decoder 1. A load circuit 13 amplifies the detection signal to be supplied to the sensing amplifier 7.
In the semiconductor memory device having the configuration shown in FIG. 1, voltages Vcc, Ve and Vss satisfy the relation Vcc&gt;Ve&gt;Vss. The voltage Vcc is set, for example, to be 5 V; Ve is set to be 3 V; and Vss is set to be the ground potential. An address signal is supplied to the decoder 1 from a computer (not shown) or the like through the address buffer circuit (not shown). For the sake of simplicity, it is assumed that the address signal designates the floating gate memory 3-1. The decoder 1 decodes this address signal. The n floating gate memories 3-1 to 3-n are connected to a line 5 through n-channel MOS transistors N1-1 to N1-n, respectively. In order to select the memory 3-1, the decoder 1 supplies a signal of H level to the gates of the n-channel MOS transistor N1-1 and the memories 3-1 to 3-n. If a signal is not written in the memory 3-1, the memory 3-1 is turned on. Since the voltage Vss is applied to the source of the memory 3-1, as shown in FIG. 1, the voltage Vd at a node between the memory 3-1 and the n-channel MOS transistor N1-1 drops. Then, the n-channel MOS transistor N1-1 is also turned on, and the voltage Vc at a node C of the line 5 and the n-channel MOS transistors N1-1 to N1-n also drops.
Meanwhile, the source of an n-channel MOS transistor N2 is connected to the line 5, and the drain thereof receives the voltage Vcc. An n-channel MOS transistor N3 (transfer gate) is inserted in series between the line 5 and the sensing amplifier 7 comprising a current mirror type differential amplifier. The sensing amplifier 7 comprises p-channel MOS transistors P1 and P2, and n-channel MOS transistors N4, N5 and N6. A bias circuit 9 consists of a p-channel MOS transistor P3 and n-channel MOS transistors N7, N8. The bias circuit 9 applies constant voltage Ve to the gates of the n-channel MOS transistors N2, N3 and N6. The n-channel MOS transistors N2 and N3 are turned on by a decrease in the voltage Vc. Then, the voltage Vb at a node B of the n-channel MOS transistor N3 and the sensing amplifier 7 also drops. The load circuit 13 connected to the node B thereto supplies a current which is determined by the ratio of the conductances of the n-channel MOS transistors N2 and N3. The voltage Vb becomes lower than a reference voltage Va which is the output voltage from the reference voltage generator 11. The sensing amplifier 7 compares the voltages Vb and Va and produces a binary signal corresponding to the comparison result (Va&gt;Vb). In other words, the sensing amplifier 7 produces a binary signal which represents that the memory 3-1 is in the non-written state. However, if a signal has been written in the memory 3-1, the memory 3-1 is OFF, even if a signal of H level is supplied to the gate thereof. The node C is charged by the n-channel MOS transistors N2 and N3; and the voltage Vc at this node C increases. However, in this case, the voltage Vc is limited to a voltage Vcc-Vthn-Vthb (Vthn is the threshold voltage of the n-channel MOS transistor when the bias of substrate is zero and Vthb is the increment of the threshold voltage due to the substrate bias effect of the n-channel MOS transistor). Therefore, the voltage Vthb is also limited to a value lower than the upper limit of the voltage Vc. A high voltage is not therefore applied to the memory 3-1 so that the memory content therein is not accidentally changed.
When the voltage Vc at the node C reaches the upper limit, the n-channel MOS transistors N2 and N3 are turned off. The node B is therefore charged, and the voltage Vb is increased to be higher than the reference voltage Va. The sensing amplifier 7 compares the voltages Vb and Va, detects that data is written in the memory 3-1, and produces a corresponding binary signal. In this manner, the load circuit 13 performs amplification on the voltage Vb at the node B.
The load circuit 13 of the conventional semiconductor memory device generally comprises an n-channel enhancement type (n-channel E-type) MOS transistor 21 having a gate and drain receiving the voltage Vcc and the source connected to the node B, as shown in FIG. 2. Alternatively, the load circuit 13 conventionally comprises a p-channel enhancement type (p-channel E-type) MOS transistor 31 having a source receiving the voltage Vcc, a gate receiving the voltage Vss, and a drain connected to the node B, as shown in FIG. 4.
The sensing amplifier 7 in the memory device of U.S. Pat. No. 4,223,394 comprises n-channel MOS transistors, which have disadvantages such as low operating speed and low sensitivity. Sensing amplifier 7 may alternatively comprise CMOS transistors. The inventors measured the characteristics of such a memory device with a sensing amplifier of CMOS transistors and a conventional load circuit.
FIG. 3 shows an example of the relationship between the voltage Vd, the voltage Vb, a current IN1 flowing in the n-channel MOS transistor N1-1, and a current I1 flowing in the memory 3-1 in the unwritten state, when the MOS transistor 21 is used as the load circuit 13
and the sensing amplifier comprises CMOS transistors. A voltage VbL corresponding to point F3 where the currents IN1 and I1 coincide appears at the node B when a signal is not written in the memory 3-1. When a signal is written in the memory 3-1, the voltage Vb at the node B is increased to only Vcc-Vthn-Vthb (VbH) (Vthn is the threshold voltage of the n-channel MOS transistor when the bias of substrate is zero and Vthb is the increment of the threshold voltage due to the substrate bias effect of the n-channel MOS transistor). In general, the voltage drop due to the substrate bias effect of the n-channel MOS transistor is great. Therefore, the level width of the voltage Vb at the node B (the difference between the voltages VbL and VbH) is small, for example, in FIG. 3, VbL is 2 V, and VbH is 2.8 V. The sensing amplifier 7 must therefore be able to sense a small voltage difference between the reference voltage Va and the voltage Vb. The sensing amplifier 7 must therefore have high sensitivity and high precision. It is therefore difficult to design and manufacture the sensing amplifier 7. Moreover, the sensing amplifier 7 is susceptible to the adverse effect of noise. The operation speed of the sensing amplifier 7 and hence that of the semiconductor memory device shown in FIG. 1 will be lower.
FIG. 5 shows the relationship between the voltage Vd, the voltage Vb, the current IN1 flowing in the n-channel MOS transistor N1-1, and the current I1 flowing to the memory 3-1 in which no signal is written, when the p-channel MOS transistor 31 is used as the load circuit 13
and the sensing amplifier comprises CMOS transistors. The p-channel MOS transistor 31 operates in a triode region. As shown in FIG. 5, the voltage Vb changes significantly in accordance with changes in the process parameters and also with changes in the current I1. When the current I1 changes to I1-A, the voltage Vb supplied to the sensing amplifier 7 largely deviates from the voltage VbL and becomes VbA, due to manufacturing variations in the memory 3-1. This renders the selection and setting of the reference voltage Va difficult. Depending upon the value of the reference voltage Va, the level VbL of the voltage Vb cannot be detected, and a correct output signal cannot be obtained. The operating speed of the sensing amplifier may also vary. The precision of each element constituting the semiconductor memory device must be increased.
EPROMs, RAMs and the like have become more highly integrated recently. With such a trend, the actual amount of the signal carriers to be stored in a memory cell of the PROM or RAM is decreased. For this reason, a semiconductor memory device capable of detecting a signal of small magnitude written in the memory cell and of producing a corresponding binary signal with high precision is required.
A EPROM with a sensing amplifier consisting of a differential amplifier comprising CMOS transistors has not yet been proposed. It is therefore generally necessary to select a semiconductor memory device having an optimal circuit configuration from those having sense amplifiers consisting of CMOS transistors.